Method of Making an Integrated Circuit

ABSTRACT

A method is provided for making an integrated circuit. Cell representing a layout of a set of features, is divided into at least a first region and a second region. Optical Proximity Correction is carried out on at least the first region of cell. One or more instances of cell are located to define IC prior to carrying out final OPC optimisation on the second regions of each cell in the defined IC.

FIELD OF THE INVENTION

The present invention relates to a method of making an integratedcircuit.

BACKGROUND OF THE INVENTION

When making an integrated circuit (which may also be referred to as achip or device), photolithography is used to transfer features from areticle or mask to a semiconductor wafer. Since photolithography istypically not able to faithfully reproduce the reticle design on thewafer, the reticle design is adjusted or optimised so that the featureson the semiconductor wafer are created at the desired dimensions. Todetermine and form the optimised reticle design, the area around afeature on the reticle design must be considered. Techniques such asoptical proximity correction (OPC) may be used. The OPC procedure isused to compensate for such optical effects as diffraction, forinstance. Such effects may lead to rounded corners of features on thefinal silicon wafer, or to a reduction in gaps between adjacent featureswhich are outside of process tolerances. The optical influence thatfeatures have on their neighbours falls off rapidly as the distancebetween the features increases. For features on the final chip that areapart by more than several wavelengths of the light used to form theimage on the silicon wafer, the influence may be disregarded. Thiscorresponds to a separation of features greater than approximately 1 to3 μm for ultraviolet light.

The OPC procedure is usually carried out after the design and layout ofthe integrated circuit has been determined and so is carried out as oneof the final steps before the reticle is produced. The OPC procedure istypically carried out using a powerful computer system. Execution timesrange from several hours to several days depending on the size of thedesign and the computing power available.

The OPC stage may include a rule based procedure, for instance. Suchrules may enlarge the ends of tracks to form hammerheads and extend theouter portions of corners whilst reducing the inner portions, forinstance. Model based techniques may also follow. These simulate theresultant optical image formed by the reticle exposure onto the siliconwafer and iteratively correct any abnormal features. Normally, severaliterations of OPC calculations are required in order to sufficientlyoptimise a reticle design, i.e. such that features on the semiconductorwafer are created at the correct dimensions.

As the OPC procedure must be carried out at the end of the design stage,the computer runtime used to perform it adds to the overall deliverytime of the final integrated circuit. As the need to increase the numberof features on an integrated circuit grows, so too will the OPCcalculation runtime. Similarly, as the feature size on integratedcircuits decrease, higher tolerances will be required to ensurereliability of the resultant devices. The execution runtime problem willcontinue to get worse as OPC calculations must be carried out on currentcomputers, which must be used to optimise tomorrow's processors.

In order to improve the integrated circuit design process repeatedfeatures such as those forming memory or logic blocks, for instance, aregrouped together in cells. This allows designers to reuse previousdesigns and fragments of designs. In this way, pallets of cells may formlarge libraries to be incorporated within future integrated circuits.

Several approaches have been tried to minimize the runtime of the finalOPC calculation step:

U.S. Pat. No. 6,807,663 describes the use of OPC pre-processing to speedup the final OPC calculation procedure. Repeating structures are foundrepresenting cells or parts of cells. OPC calculations are carried outon these repeating structures individually. This is performed before thefinal chip layout has been constructed. Each cell contains a coresurrounded by an empty border region which has a width equal to theproximity range (the distance within which neighbouring features willinterfere optically). Cell cores therefore, have a border of dead spacearound them so that once OPC calculations have been carried out on acell, such OPC calculations do not need to be repeated once the cell isincorporated into a chip design. In other words, the OPC result for acell in isolation will be the same at that for a cell located within theintegrated circuit. This approach has the drawback that empty space thatcould otherwise be used for more features is wasted on each chip layer.

Similarly, U.S. Pat. No. 5,682,323 also uses a large library of cellsthat have already had OPC calculations carried out on them. These cellsare placed within the chip design and are each surrounded by empty spaceso that no proximity affects occur. This has the same drawbacks as thosementioned above.

U.S. Pat. No. 6,425,117 also teaches the method of carrying out OPCcalculations on individual cells within a library. These cells are thenplaced within the integrated circuit design no closer than a minimumdistance to ensure that no proximity effects will occur between elementsalready optimised and corrected. Features on the chip that fall outsideof the cell boundaries have additional OPC calculations carried out onthem. Again, this leads to wasted space on the chip design.

U.S. Pat. No. 6,194,252 describes the method of carrying out OPCcalculations on individual cells before placement in the integratedcircuit design. However, when carrying out these pre-calculations dummyfeatures are placed around each cell. This attempts to simulate theenvironment once the cell is placed within the integrated circuit. Thistechnique has the drawback that the resultant corrections are onlyestimations as the dummy features will not be the same as the realneighbouring features on the final chip layout. This can lead to errorsin the final OPC result and even faults on the device.

It is therefore desirable to provide a method for making an integratedcircuit that enables OPC optimisation to be performed with increasedaccuracy early in the design process.

SUMMARY OF THE INVENTION

In accordance with a first aspect of the invention, there is provided amethod of making an integrated circuit as recited in claim 1 of theaccompanying claims. The advantage of this method is to maximise theamount of OPC optimisation carried out on portions of the integratedcircuit early on in the design process. This has the benefit ofdecreasing the time taken to perform the final OPC optimisation step onthe completed integrated circuit layout.

Optionally, method step (b) may further comprise the step of: (iii)determining a quantity of additional OPC calculations that will berequired for each of the first region and the second region of the cellafter the cell is incorporated into the integrated circuit, and whereinthe quantity of OPC calculations performed in step (d) is the quantityof additional OPC calculations determined in step (iii). This allows theamount of additional OPC calculations required, to be known when thefinal OPC run is performed.

Preferably, the quantity of additional OPC calculations found in step(iii) of the method for the first region is zero. This allows full OPCoptimisation to be carried out on the first region of each cell and sofurther reduces the time taken to perform the final OPC optimisationstep on the completed integrated circuit layout.

Preferably, determining the quantity of additional OPC calculationsdepends on the distance between at least one of the first region and thesecond region and an edge of the cell. This enables multiple regions tobe defined in excess of the first and second regions, each requiring adifferent amount of OPC optimisation to be carried out on the featurescontained within them. Regions located closer to the edge of the cell(outer regions) will require more OPC optimisation during the final OPCrun, as the features contained within the outer regions will beinfluenced more by features surrounding the cell. It is therefore, notnecessary to carry out many OPC iterations on the outer regions when thecell is optimised in isolation.

Advantageously, the amount of additional OPC calculations that will berequired for the first region and the second region is a number of OPCiterations. This enables the number of additional OPC iterationsrequired by each region of the cell to be defined and stored within alibrary of cells.

Advantageously, the second region extends a predetermined distance froman edge of the at least one cell. This allows the cell to be dividedinto separate regions automatically.

Preferably, the second region surrounds the first region. Thissimplifies the division of the cell.

Optionally, step (ii) may include performing OPC calculations on allregions of the cell. This simplifies the OPC optimisation carried out onthe cell in isolation and allows the cell to be divided into regionsafter the cell has been optimised.

Advantageously, the method may further comprise the step of: (d) addingthe cell (200) to a library of cells. This allows reuse of cells withincurrent and future integrated circuits.

Optionally, step (b) may further comprise the step of: (iv)distinguishing the first region from the second region using one of amarker layer, an edge tag and a feature property. This enables thephysical extent of the first and second regions to be recorded.

Optionally, the method may further comprise the step of calculating anexpected OPC execution time prior to step (d). This allows the designerto allocated sufficient computing resources to complete the OPCoptimisation.

Optionally, the method may further comprise the step of identifyingthose features which require fewer OPC calculations and locating themremote from the first region. This further reduces the final OPCoptimisation runtime as features requiring more OPC optimisation may belocated preferentially within the first region, which is optimised atthe cell optimisation step.

Optionally, the library of cells may contain cells that have featuresthat require fewer OPC calculations preferentially arranged closer to anedge of the cell than features that require more OPC calculations. Thisfurther reduces the final OPC optimisation runtime as features requiringmore OPC optimisation may be located preferentially within the firstregion, which is optimised at the cell optimisation step.

Optionally, method step (b) may further comprise the step of (v)identifying any errors in the integrated circuit. As OPC optimisation iscarried out at the cell level any errors may be identified during thisearly stage and before the final OPC run.

Optionally, the errors found may include any of OPC errors and criticaldimension variation errors. OPC errors include forming gaps orconnections on the resultant device that are too small to manufacturereliably. Critical dimension variation errors include systematicdifferences in critical dimension of features occurring across thedevice due to optical effects of the reticle exposure, for instance.

Optionally, step (b) may further comprise the step: (vi) performing OPCcalculations on the second region. This allows partial or full OPCoptimisation to be carried out on the entire cell including the firstand second regions and any further regions defined. This further reducesthe time required for performing the final OPC optimisation carried outon the entire integrated circuit. The amount of OPC optimisation carriedout during this step may be limited to some extent or carried out infull. Any such limits may be predetermined. A different amount of OPCoptimisation may be carried out on the first and second regionsrespectively, during this step. Typically, more iterations of OPCoptimisation may be required for the first region than for the secondregion during this step as the first region may not be optimised at allduring subsequent final OPC optimisation or may only be optimised by asmall amount.

Optionally, the method may further comprise the step: performing OPCcalculations on the first region of the or each cell in the definedintegrated circuit after step (c). The first region may require furtherOPC fine tuning once the cell has been placed in the integrated circuit.Such fine tuning may be carried out in this step. This step may becarried out before or after step (d). A different amount of OPCoptimisation may be carried out on the first and second regionsrespectively, during the final OPC optimisation step.

Optionally, the first region may be a central region and the secondregion may be peripheral region.

Optionally, the first region may be described as a low sensitivityregion, whereby features located within this first region may not besensitive to optical effects due to the distance of this region fromareas on the integrated circuit outside of the cell. The low sensitivityregion will be surrounded by or be close to areas on the cell orintegrated circuit that will not change significantly followingplacement of the cell within the integrated circuit layout.

Optionally, the second region may be described as a high sensitivityregion, whereby features located within this second region may besensitive to optical effects due to its proximity with areas on theintegrated circuit that are likely to change significantly.

The first region of the cell and the second region of the cell containfeatures. These features are part of the cell.

BRIEF DESCRIPTION OF THE FIGURES

The present invention may be put into practice in a number of ways and apreferred embodiment will now be described by way of example only andwith reference to the accompanying drawings, in which:

FIG. 1 shows a flow diagram of a method for making an integrated circuitin accordance with the present invention, including the steps fordesigning a cell;

FIG. 2 shows a schematic diagram of the cell used in the method shown inFIG. 1, including a high sensitivity region; and

FIG. 3 shows a schematic diagram of a portion of the integrated circuitused in the method shown in of FIG. 1 including more than one cell.

It should be noted that the figures are illustrated for simplicity andare not necessarily drawn to scale.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

FIG. 1 shows a flow chart describing a method for making an integratedcircuit according to one aspect of the present invention. The flow chartdoes not show all of the steps for making an integrated circuit butthese remaining steps will be familiar to the skilled person. Theprocess starts with the design of a layout of a cell, step 20. Each cellrepresents a layout of a set of features to be incorporated in anintegrated circuit, e.g. gates of memory cells. Cells are portions ofthe integrated circuit which may be repeated many times within the finaldesign. For instance, memory cells or core cells may be used manythousands of times within a particular integrated circuit. Once thelayout of the cell has been finalised, it may be easily duplicatedwithin the integrated circuit. Next at step 30, the cell is divided intoa low sensitivity region and a high sensitivity region. Features withinthe low sensitivity region will be far enough from the edge of the cellto ensure that any optical interaction between these features andfeatures of neighbouring cells can be ignored, i.e. outside of theproximity distance. The low sensitivity region contains features thathave a low sensitivity, with regard to optical effects, to featuresplaced around the cell. This may be because of the distance between thelow sensitivity region and the features around the cell or that thefeatures within the low sensitivity region have physical attributes thatreduce the impact of any optical effects. For instance, the features maybe large in comparison to neighbouring features. Specifically, thesefeatures may be large interconnect features, for instance. However,other features of the cell may be located within the high sensitivityregion. The high sensitivity region will contain features that arehighly sensitive to features placed around the cell. The reason for thishigh sensitivity may be because of the proximity of the high sensitivityregion to the features around the cell (which may be immediatelyadjacent to them) or that the features within the high sensitivityregion contain structures that are sensitive to optical effects andwhich, therefore, require higher OPC accuracy.

Features within the high sensitivity region of the cell may be affectedoptically by features of neighbouring cells or other features on theintegrated circuit. The structure of a cell and the shape and size ofthe low sensitivity and high sensitivity regions will be discussed withreference to FIG. 2.

Next at step 40, OPC calculations may be carried but by an OPC tooloperating on a computer, to fully optimise the features of the lowsensitivity region of the cell. Such OPC tools, for example Proteus(RTM) supported by Synopsys (RTM), inc. of Mountain View, Calif., USA,are familiar to the skilled person and so do not require any furthercomment. This may require several iterations of calculations until adesign is achieved that contains features that are of suitabledimensions. As the low sensitivity region is located far enough from theedge of the cell for its features to avoid any interactions withneighbouring cells or other features outside of the cell itself, the lowsensitivity region of the cell will not require any further OPCcalculations once the cell has been placed within the chip design. Thefeatures within the low sensitivity regions will be optically affectedby features within the high sensitivity region of the cell (if there areany present) but these interactions will be fully considered during theinitial OPC optimisation step carried out on the cell in isolation (step40).

Next at step 50, partial OPC calculations are carried out on the highsensitivity region. Because the features located in the high sensitivityregion may be affected by other as yet unknown, bordering features orother cells, it is not possible to obtain full OPC results for thisregion at this stage. Therefore, it is not necessary to fully optimisethe features within the high sensitivity region (this will need to berepeated once the cell is incorporated in the layout of the device, inany case). Whilst carrying out OPC calculations, errors in the designmay be found by the OPC tool or other software. Such errors that may beidentified may include features that are too close together or featuresthat do not overlap enough (e.g. gates and contacts). The next step is,therefore, to search for any errors, step 60. If errors are detected,step 70, they are fixed, step 75, and the layout of the cell may changeor the OPC process may be adjusted and further OPC calculations may berequired on the cell. Therefore, steps 40 to 70 will need to be repeateduntil no errors are found.

Once a cell layout has been finalised and all necessary OPC calculationshave been carried out, the data describing the physical properties ofthe cell, including the geometries of all of the features and segments(portions added to the features during OPC processing), may be added toa library of other finalised cells, step 80. The library forms a palletof cells that a designer may use to build the integrated circuit layout.

Once the designer has designed the full integrated circuit using cellsfrom the library (step 90) as well as other necessary features such asconnectors, it will be possible to estimate the total runtime necessaryfor the final OPC execution. Such a final OPC run is necessary tooptimise all of the features within each cell high sensitivity regionand any other features not already optimised (this should not berequired for any low sensitivity region on any cell). The calculation ofestimated OPC runtime step 100 is optional but will be of use to thedesigner when allocating necessary computing resources as well asproviding an indication of the delivery time of the final integratedcircuit. With prior art methods, it is difficult to obtain an accurateestimate of runtime as many calculations within the final OPC step 110are required. However, as many of the OPC calculations have already beenfinalised, the present invention provides a more accurate estimate offinal OPC runtime. A further step, 120, may optionally be carried outthat tests the effect of the OPC optimisation on the high sensitivityregions on the low sensitivity regions. This step may be required due tophysical changes made to the high sensitivity regions during OPCoptimisation. Although these changes may be small they may effect thefeatures of the low sensitivity regions, which were optimised when thehigh sensitivity regions had slightly different layouts.

FIG. 2 shows a schematic diagram for an example cell 200. The cell 200has a low sensitivity region 250 and a high sensitivity region 240 andthe cell has an edge 260. The cell contains several features of whichfeature 270 is an example. Feature 270 has a border 210 showing theoriginal extent of feature 270 prior to any OPC optimisation. Feature270 also has a corrected border 220 showing the extent of the feature270 after OPC calculations have been completed. Corrected border 220includes additional segments added during OPC optimisation.

In FIG. 2, the cell 200 is substantially square but can be any shapeincluding rectangular, oval or circular. The low sensitivity region 250is surrounded by the high sensitivity region 240. The width 280 of thehigh sensitivity region 240 is determined by the distance within whichfeatures interfere with each other optically, i.e. the proximitydistance. This distance may be determined experimentally, calculated orobserved from carrying out repeated OPC calculations.

Any features 270 within the low sensitivity region 250 will have fullOPC optimisation carried out on them before adding the cell 200 to thecell library. Any features within the high sensitivity region 240 mayhave none or some OPC calculations carried out on them during thepartial OPC step 50. The layout of the cell together with the details ofany changes made during OPC optimisation is stored in any suitable fileformat within the cell library. These file formats may include theGDS-II format.

FIG. 3 shows a schematic diagram of a portion of an integrated circuit300. This portion 300 includes two cells 340 and 350. Various featuresare shown including metallic contacts 320, overlapping portions 330forming gate electrodes and connection tracks 310.

When performing OPC optimisation the feature type may be considered bythe OPC tool in order to determine the amount and/or type of OPCoptimisation to be carried out. For instance, a device may tolerate morephysical distortion to connection tracks 310 and so these features willrequire less OPC optimisation. Conversely, overlapping features 330 suchas gate electrodes or metallic connections 320 will have a minimumcritical dimension (CD) that must be met to ensure proper function.These types of features require finer tolerances to ensure properoverlap, which in turn require more OPC optimisation or iterations to beperformed. Such features are known as critical regions. The final OPCstep 110 runtime can be minimised by maximising the amount of OPCoptimisation carried out before the cell is added to the library 80.Therefore, carrying out full OPC optimisation of features requiringfiner tolerances during step 40 (full OPC optimisation on the lowsensitivity region of the cell) will further decrease final OPC runtime.

In order to achieve this reduction in final OPC runtime, a furtherembodiment of the present invention involves locating cell 350components requiring less OPC optimisation, such as connection tracks310, for instance, within the high sensitivity region 240, wherepossible, and locating features requiring more OPC optimisation withinthe low sensitivity region 250. Obviously, this may only be achievedwhere physical constraints can be met. This is an additional designconstraint that may be implemented manually by the designer whenbuilding the layout of a cell or may be performed automatically by adesign aid such as a computer aided design program. The effect of thisadditional design constraint is that a higher proportion of full OPCoptimisation is carried out (all features located within the lowsensitivity region 250 will undergo full OPC optimisation) on featuresrequiring finer tolerances.

As will be appreciated by the skilled person, details of the aboveembodiment may be varied without departing from the scope of the presentinvention, as defined by the appended claims.

For example, any lithographic technique may be employed includingultraviolet, deep ultraviolet, extreme ultraviolet, X-ray and electronprojection lithography. The cell may be divided into more than tworegions. This could include 3, 4, 5 or more concentric regions. Also,the regions need not be concentric and may include other layouts such asseparate islands within each cell of different shapes such as squares,rectangles or circles.

As an alternative, step 50 of the method (partial OPC on highsensitivity region) may be removed as OPC optimisation is carried out onthe high sensitivity regions of all cells (step 110) once the integratedcircuit layout has been finalised (step 90).

1. A method of making an integrated circuit comprising the steps of: (a)providing a cell representing a layout of a set of features to beincorporated into an integrated circuit; (b) performing opticalproximity correction calculations on the cell comprising the followingsteps: (i) dividing the cell into a first region and a second region(ii) performing OPC calculations on at least the first region, and (iii)determining a quantity of additional OPC calculations that will berequired for each of the first region and the second region of the cellafter the cell is incorporated into the integrated circuit; (c) locatingone or more instances of the cell to define the integrated circuit; and(d) performing the quantity of OPC calculations determined in step (iii)on the second region of the or each cell in the defined integratedcircuit.
 2. The method of claim 1 wherein the quantity of additional OPCcalculations found in step (iii) for the first region is zero.
 3. Themethod of claim 1, wherein determining the quantity of additional OPCcalculations depends on the distance between at least one of the firstregion and the second region and an edge of the cell.
 4. The method ofclaim 1, wherein the amount of additional OPC calculations that will berequired for the first region and the second region is a number of OPCiterations.
 5. The method of claim 1, wherein the second region extendsa predetermined distance from an edge of the at least one cell.
 6. Themethod of claim 1, wherein the second region surrounds the first region.7. The method of claim 1, wherein step (ii) includes performing OPCcalculations on all regions of the cell.
 8. The method of claim 1,wherein adding the cell to a library of cells.
 9. The method of anyprevious claim 1 wherein step (b) further comprises the step of: (iv)distinguishing the first region from the second region using one or moreof a marker layer, an edge tag and a feature property.
 10. The method ofclaim 1, wherein calculating an expected OPC execution time prior tostep (d).
 11. The method of any previous claim 1 wherein identifyingthose features which require fewer OPC calculations and locating themremote from the first region.
 12. The method of claim 8 wherein thelibrary of cells contains cells that have features that require fewerOPC calculations preferentially arranged closer to an edge of each cellthan features that require more OPC calculations.
 13. The method ofclaim 1, wherein step (b) further comprises the step of: (v) identifyingany errors in the integrated circuit.
 14. The method of claim 13,wherein the errors including any of OPC errors and critical dimensionvariation errors.
 15. The method of claim 1, wherein step (b) furthercomprises the step: (vi) performing OPC calculations on the secondregion.
 16. The method of claim 1, further comprising the step:performing OPC calculations on the first region of the or each cell inthe defined integrated circuit after step (c). 17.-19. (canceled)
 20. Anintegrated circuit manufactured according to the method of claim 1further comprising: manufacturing the integrated circuit.
 21. The methodof claim 2, wherein determining the quantity of additional OPCcalculations depends on the distance between at least one of the firstregion and the second region and an edge of the cell.
 22. The method ofclaim 2, wherein the amount of additional OPC calculations that will berequired for the first region and the second region is a number of OPCiterations.
 23. A computer-readable medium comprising instruction whoseexecution causes the performance of: (a) performing optical proximitycorrection calculations on a cell representing a layout of a set offeatures to be incorporated into an integrated circuit, the performingincluding the following steps: (i) dividing the cell into a first regionand a second region, (ii) performing OPC calculations on at least thefirst region, and (iii) determining a quantity of additional OPCcalculations that will be required for each of the first region and thesecond region of the cell after the cell is incorporated into theintegrated circuit; (b) locating one or more instances of the cell todefine the integrated circuit; and (c) performing the quantity of OPCcalculations determined in step (iii) on the second region of the oreach cell in the defined integrated circuit.